MIPI I3C incorporates key attributes of the traditional I2C and SPI interfaces to provide a unified, high-performing, very-low-power solution and delivers a robust, flexible upgrade path to I3C for I2C and SPI implementers. While I3C v1.0 delivered new capabilities to integrate mechanical, motion, biometric, environmental and any other type of sensor, MIPI I3C v1.1 (now v1.1.1) built on that capability by adding new features for peripheral command, control and communication to a host processor over a short distance and system manageability.
MIPI I3C technology is implemented on a standard CMOS I/O. It uses a two-wire interface, which reduces pin count and signal paths to offer system designers less complexity and more flexibility. It can also be used as a sideband interface to further reduce pin count. MIPI I3C supports a typical data rate of 10 Megabits per second (Mbps) with options for higher-performance high-data-rate modes, offering a substantial leap in performance and power efficiency compared with previous options. The latest version provides for extensible use of extra bus lanes to increase the interface speed, enabling new use cases and future proofing the interface as speed requirements rise. 2b1af7f3a8